Semiconductor memory devices generally include a cell array region and a peripheral circuit region. The cell array region is formed by repeatedly applying the same pattern to the device, whereas a number of different patterns may be applied in the peripheral circuit region. Typically, the level of integration achieved in the cell array region is the primary factor determining the overall level of integration of the semiconductor memory device. The level of integration achieved may depend on, among other things, the minimum resolution of the process used, the depth-of-focus (DOF), and/or the exposure latitude (EL). In recent years, off-axis illumination (OAI) techniques have been introduced, which can facilitate ensuring that a minimum resolution is obtained even as the line-width of patterns is decreased. Off-axis illumination (OAI) techniques generally can provide excellent resolution and DOF and, consequently, can be used to form small pitch patterns. However, OAI techniques can have drawbacks in terms of exposure condition with respect to size, shape, and direction of patterns. As such, conventional illuminations that employ annular apertures may be used to transfer various patterns. However, the patterns provided may not be ideal depending on the shape and geometry of the patterns required. Double-exposure techniques may be used to provide improved patterns. In double-exposure techniques, a primary exposure is performed with respect to a first pattern region, and then a secondary exposure is performed with respect to a second pattern region.
FIG. 1 is a plan view of part of a conventional semiconductor memory device having a pattern region that includes patterns of two different pitches.
Many conventional semiconductor devices include a pattern region that has patterns that have two or more different pitches. By way of example, in conventional semiconductor memory devices, the cell array region may have a pattern that has a first pitch and the peripheral circuit region may include one or more patterns that have different pitches. In order to maximize the integration of the device, the memory cells in the cell array region typically have the minimum line width. In contrast, a relatively larger pitch pattern may be provided in the peripheral circuit region. For example, as shown in FIG. 1, the pattern region of the semiconductor memory device may include a first pattern 34a having a first pitch P1 and a second pattern 34b that has a second pitch P2. The second pitch P2 is larger than the first pitch P1. By dividing the semiconductor device into regions and using a double-exposure process that applies exposure conditions that may be optimized for each region, it may be possible to obtain improved patterns. For the first (primary) exposure, a region 16 in which a first pattern is formed is exposed in order to transfer the first pattern. For the second exposure, a region 26 in which a second pattern is formed is exposed in order to transfer the second pattern 34b. 
FIGS. 2A and 2B are plan views of the first mask layer 10 and the second mask layer 20, respectively, of a conventional double-exposure mask set. First mask layer 10 may be used to form the first pattern 34a depicted in FIG. 1. Second mask layer 20 may be used to form the second pattern 34b of FIG. 1. As shown by the dotted line in FIG. 2A, the first mask layer 10 includes a first screen region 11 and a first exposure region 13. The first screen region 11 is covered with a shield layer 12, whereas a first pattern 14 is formed in the first exposure region 13. As shown in FIG. 2b, the second mask layer 20 includes a second screen region 17 and a second exposure region 15. The second screen region 17 is covered with a shield layer 22, whereas a second pattern 24 is formed in the second exposure region 15. The first and second mask layers 10, 20 may be used to pattern a substrate using a double-exposure process.
Misalignment of the first and second exposures may occur in a double-exposure process. As such, the first and second mask layers 10, 20 may be formed such that the first and second exposure regions 13, 15 overlap. The overlap region forms a desired pattern by performing Optical Proximity Correction (OPC) considering the double-exposure. However, a halftone mask with high contrast may provide a poor pattern in the overlap region due to misalignment and registration at the exposure boundaries.
FIGS. 3A to 3D are plan views illustrating how misalignment and registration can impact the patterns formed using a conventional double-exposure mask set.
As shown in FIG. 3A, if misalignment and registration occur, the shield layer 12 may fail to completely cover halftone pattern 14 at a boundary of the first exposure region 13 of the first mask layer 10 (see, e.g., the region labeled F1 in FIG. 3A). Likewise, as shown in FIG. 3C, as a result of misalignment and registration the shield layer 22 may fail to completely cover halftone pattern 24 at a boundary of the second exposure region 15 of the second mask layer 20 (see, e.g., the region labeled F2 in FIG. 3B). Alternatively (or additionally), as shown in FIG. 3B, a part of the shield layer 12 may extend into the first exposure region 13 of the first mask layer 10, thereby covering a portion of the halftone pattern 14 at a boundary of the first exposure region 13 (see, e.g., the region labeled F3 in FIG. 3C). Likewise, as shown in FIG. 3D, the shield layer 22 may extend into the second exposure region 15 of the second mask layer 20, thereby covering a portion of the halftone pattern 24 at a boundary of the second exposure region 15 (see, e.g., the region labeled F4 in FIG. 3D). First and second mask layers become OPC considering the double-exposure of the overlap region. The imperfect patterns in the regions labeled F1, F2, F3 and F4 at the boundaries of the exposure regions may prevent proper exposure or induce unwanted double-exposure.